1. Field of the Invention
This invention relates to a deglitching circuit for suppressing glitches occuring on outputs of a digital/analog converter (hereinafter referred to as DAC).
2. Description of the Prior Art
In response to digital data inputted to a DAC, switching circuits of respective bits will be turned on and off. Weighted currents of the bits that have turned on the switching circuits are added to each other to output a current corresponding to the digital data. Due to differences in rise and fall times of the switching circuits, hair-like noises or glitches tend to occur on outputs of DAC. Various circuits have been proposed to suppress such glitches.
An example of conventional deglitching circuit employing a sample holding circuit is shown in FIG. 4. More particularly, a quadruple oversampling digital filter 1 outputs 16-bit serial data. In response to a shift clock SCK generated from a clock control circuit 2, the serial data are sequentially fetched by a DAC 3. When the 16-bit data are completely fetched in DAC 3, the clock control circuit 2 outputs a latch enabling signal LE. Then, DAC 3 perform digital/analog conversion to output a current corresponding to the input digital data. The current is sent to a current/voltage converting circuit comprising an operational amplifier 4 and a negative feedback resistor R.sub.1, then to a sample holding circuit 6 comprising resistors R.sub.2 and R.sub.3, a capacitor C.sub.1, an operational amplifier 7 and an analog switch 8. In response to a sample signal SMP from the clock control circuit 2, the sample holding circuit 6 samples an output of the current/voltage converting circuit 5 when no glitch occurs on the output of DAC 3 while the sample holding circuit 6 holds a sampled value during the occurrence of a glitch. An output of the sample holding circuit 6 is sent to a low-pass filter 9 for removing spurious components whose carrier is an integer multiple of a sampling frequency, from the output of the sample holding circuit 6. Then, an output is given at an output terminal T.sub.1 of the low-pass filter 9.
According to the deglitching circuit of FIG. 4, the analog switch 8 may cause switching noises to be included in output signals, and the capacitor C.sub.1 may deteriorate the sound quality. Thus, fine signals from DAC 3 would often be hidden behind the noises.
FIG. 5 shown another example of conventional deglitching circuit disclosed in the U.S. Pat. No. 4,814,740. In this deglitching circuit, 16-bit serial data is outputted from a quadruple oversampling digital filter 10. In response to a shift clock SCK from a clock control circuit 11, the serial data are sequentially fetched by a serial/parallel converting circuit 12. When the 16-bit data are completely fetched by the circuit 12, the clock control circuit 11 outputs a latch clock RCK so that the 16-bit data may be converted into parallel data. Outputs terminals O.sub.1 to O.sub.16 of the serial/parallel converting circuit 12 are connected to input terminals MSB to LSB of a DAC 13 through resistors R.sub.11 to R.sub.26, respectively. DAC 13 converts inputted digital data into parallel data and outputs a current corresponding to the inputted data. DAC 13 is PCM54KP of Burr Brown. This DAC has different circuit arrangements for upper 3 bits and for lower 13 bits. Accordingly, rise (fall) times of switching circuits for the upper 3 bits substantially agree with each other, while rise (fall) times of switching circuits for the lower 13 bits substantially agree with each other. However, the rise (fall) times of the switching circuits for the upper 3 bits and for the lower 13 bits are different from each other. Consequently, even if the serial/parallel converting circuit 12 outputs digital signals whose rise and fall times agree with each other, an output of DAC 13 will contain glitches.
To deal with this problem, the input terminals MSB to 3SB of DAC 13 are connected to a variable voltage source V.sub.1 through resistors R.sub.27 to R.sub.29 to adjust threshold voltages for turning on and off the switching circuits for the upper 3 bits of DAC 13. Similarly, to adjust threshold voltages of the lower 13 bits, only the input terminals 4SB to 9SB that particularly tend to cause glitches are connected to a variable voltage source V.sub.2 through resistors R.sub.30 to R.sub.34. The variable voltage sources V.sub.1 and V.sub.2 are respectively adjusted to make the rise (fall) times of the upper 9 bits agree with each other so that an output of DAC 13 may accompany no glitch. A current output of DAC 13 is converted into a voltage by a current/voltage converting circuit 15 comprising an operational amplifier 14 and a negative feedback resistor R.sub.35. A low-pass filter 16 will remove spurious components of the voltage output of the current/voltage converting circuit 15. An output is thus given at an output terminal T.sub.2 of the low-pass filter 16.
The glitch suppressing circuit of FIG. 5 is effective to overcome drawbacks of the example of FIG. 4. However, since this deglitching circuit employs the serial/parallel converting circuit, it will not be applicable for a DAC designed to directly input serial data.